1. Field of the Invention
This invention relates generally to random access memory, and more particularly to gate training in memory interfaces.
2. Description of the Related Art
Double data rate (DDR) synchronous dynamic random access memory (SDRAM) is a class of memory capable of providing approximately twice the bandwidth of single data rate SDRAM. DDR SDRAM achieves this increased bandwidth without requiring an increased clock frequency by transferring data on both the rising and falling edges of the clock signal. Because the increased bandwidth, DDR SDRAM often is used in the design of integrated circuits.
In order to compensate for the high data throughput of DDR SDRAM, DDR SDRAM utilizes a data strobe signal to transfer data on each rising and falling edge of the data strobe signal. To coordinate the transfer of data to and from a DDR SDRAM memory device, a synchronization circuit in the form of a memory controller often is used with the memory device. The memory controller uses the data strobe signal for determining when the read data is valid and can therefore be latched. The times at which the read data is latched are preferably synchronized relative to the data strobe signal so as to latch the read data in the middle of valid data window.
The data strobe signal generated by the memory device with the read data has predefined phase constraints with respect to the local clock signal provided by memory controller. In particular, the data strobe generally is phased such that the transitions of the data strobe from HIGH to LOW or LOW to HIGH are centered in each window of data transferred on the data bus. In addition, because the data strobe bus is bi-directional, the data strobe bus is gated to avoid inadvertent clock pulses from reaching the data latching logic.
FIG. 1 is a block diagram showing a prior art data strobe gate and phase shift circuit 100. The prior art data strobe gate and phase shift circuit 100 includes an AND gate 102 having a data strobe (DQS) line 104 and a DQS gate line 106 as input. During a read operation, the data strobe signal from the memory device is provided on the DQS line 104 and the memory controller provides DQS gate signal on the DQS gate line 106. The output of the AND gate 102 is the post AND gate DQS line 107, which is provided as input to a phase shift logic circuit 108. The phase shift logic circuit 108 generally phase shifts the post AND gate DQS line 107 ninety degrees and outputs the phase shifted DQS signal on the phase shifted DQS line 110. In this manner, the signal provided on the phase shifted DQS line 110 is the gated DQS signal from the memory device phase shifted ninety degrees so as to have transition centered in each window of data transferred on the data bus, as illustrated next with reference to FIG. 2A.
FIG. 2A is a timing diagram for the prior art data strobe gate and phase shift circuit 100 of FIG. 1. As illustrated in FIG. 2A, the timing signals include an internal clock signal 200 of the memory controller, a data (DQ) signal 202 providing the read data from the memory device, a data strobe (DQS) signal 204 from the memory device, a data strobe gate (DQS_gate) signal 206, and a phase shifted DQS signal 208 provided from the data strobe gate and phase shift circuit 100 of FIG. 1.
The read data protocol for DDR memories is source synchronous. Thus, the DQS signal 204 initially is aligned with the read data 202 when sent to the memory controller. For example, in FIG. 2A, the read data 202 includes four beats of data, zero, one, two, and three, wherein a beat refers to data transferred during a single half clock cycle. In addition, the DQS signal 204 is sent edge aligned with the read data 202. As illustrated in FIG. 2A, the DQS signal 204 includes a one clock period preamble 204a followed by four transitions, each edge aligned with the data 202, followed by a postamble 204b. During the preamble 204a and postamble 204b the DQS signal 204 is driven LOW by the memory device.
Before the preamble 204a and after the postamble 204b, the DQS signal 204 is at a tri-state level, which is a high-impedance state that allows other devices to drive the bus. However, when at the tri-state level, the value of the DQS signal 204 is unpredictable. Hence, the DQS_gate signal 206 is used to gate the DQS signal 204. As illustrated in FIG. 2A, the DQS_gate signal 206 is opened (i.e., asserted) during the preamble 204a of the DQS signal 204, and closed during the postamble 204b. In this manner, the output of the AND gate 102 of FIG. 1 is LOW when the DQS_gate signal 206 is LOW, and follows the transitions of the DQS signal 204 when the DQS_gate signal 206 is HIGH.
As discussed with reference to FIG. 1, the post AND gate DQS signal on line 107 is phased shifted ninety degrees, resulting in the phase shifted DQS signal 208 shown in FIG. 2A. In this manner, ideally the beat zero data is latched on the first rising edge of the phase shifted DQS signal 208, the beat one data is latched on the first falling edge, the beat two data is latched on the second rising edge, and the beat three data is latched on the second falling edge of the phase shifted DQS signal 208. However, this results depends on the DQS_gate signal 206 being properly placed (i.e., asserted) in the preamble 204a of the DQS signal 204 during the data read operation. If the DQS_gate signal 206 is not properly asserted in the preamble 204a problems can occur resulting in lost data or false data being latched, as illustrated next with reference to FIG. 2B.
FIG. 2B is a timing diagram for the prior art data strobe gate and phase shift circuit 100 of FIG. 1, wherein the DQS_gate signal 206′ is asserted improperly. In particular, FIG. 2B illustrates an example of timing signals resulting from asserting the DQS_gate signal 206′ too early, prior to the preamble 204a of the DQS signal 204. As illustrated in FIG. 2B, when the DQS_gate signal 206′ is asserted, the DQS signal 204 is still at the tri-state level. As a result, the state of the phase shifted DQS signal 208′ is set at an unpredictable state. For example, FIG. 2B illustrates the phase shifted DQS signal 208′ going HIGH as the DQS_gate 206′ is asserted. Then, the preamble 204a causes the phase shifted DQS signal 208′ to go LOW. Next, the beat zero data is latched on the first rising edge of the phase shifted DQS signal 208′, but the phase shifted DQS signal 208′ goes LOW and stays LOW when the DQS_gate signal 206′ goes LOW. Consequently, the beat one data also is latched but the remaining beats of data, beats two and three, are lost. Other poor results occur when the DQS_gate is asserted too late, after the preamble 204a. 
In view of the foregoing, there is a need for systems and methods for gate training in memory interfaces such that the gate signal is properly asserted in the preamble of the data strobe signal. Ideally, the gate signal should be asserted in the middle of the preamble, and should be automated so as not to require manual placement. Moreover, the systems and methods should allow for correction of the gate signal when drift occurs over time, and should take into account write leveling delays caused by fly-by topologies of newer DDR SDRAM DIMM architectures.